| A 167-processor computational platform in 65 nm CMOS DN Truong, WH Cheng, T Mohsenin, Z Yu, AT Jacobson, G Landge, ... Solid-State Circuits, IEEE Journal of 44 (4), 1130-1144, 2009 | 313 | 2009 |
| A low-complexity message-passing algorithm for reduced routing congestion in LDPC decoders T Mohsenin, DN Truong, BM Baas IEEE Transactions on Circuits and Systems I: Regular Papers 57 (5), 1048-1061, 2010 | 129 | 2010 |
| AsAP: An asynchronous array of simple processors Z Yu, MJ Meeuwsen, RW Apperson, O Sattari, M Lai, JW Webb, EW Work, ... Solid-State Circuits, IEEE Journal of 43 (3), 695-705, 2008 | 114 | 2008 |
| A 167-processor 65 nm computational platform with per-processor dynamic supply voltage and dynamic clock frequency scaling D Truong, W Cheng, T Mohsenin, Z Yu, T Jacobson, G Landge, ... VLSI Circuits, 2008 IEEE Symposium on, 22-23, 2008 | 90 | 2008 |
| The design of a reconfigurable continuous-flow mixed-radix FFT processor AT Jacobson, DN Truong, BM Baas 2009 IEEE International Symposium on Circuits and Systems, 1133-1136, 2009 | 58 | 2009 |
| A reconfigurable source-synchronous on-chip network for GALS many-core platforms AT Tran, DN Truong, B Baas IEEE transactions on computer-aided design of integrated circuits and …, 2010 | 53 | 2010 |
| AsAP: A fine-grained many-core platform for DSP applications B Baas, Z Yu, M Meeuwsen, O Sattari, R Apperson, E Work, J Webb, ... Micro, IEEE 27 (2), 34-45, 2007 | 49 | 2007 |
| A complete real-time 802.11 a baseband receiver implemented on an array of programmable processors AT Tran, DN Truong, BM Baas Signals, Systems and Computers, 2008 42nd Asilomar Conference on, 165-170, 2008 | 40 | 2008 |
| Multi-split-row threshold decoding implementations for LDPC codes T Mohsenin, D Truong, B Baas Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on …, 2009 | 32 | 2009 |
| A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network AT Tran, DN Truong, BM Baas 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, 214-223, 2009 | 26 | 2009 |
| A low-cost high-speed source-synchronous interconnection technique for GALS chip multiprocessors AT Tran, DN Truong, BM Baas 2009 IEEE International Symposium on Circuits and Systems, 996-999, 2009 | 15 | 2009 |
| An improved Split-Row Threshold decoding algorithm for LDPC codes T Mohsenin, D Truong, B Baas Communications, 2009. ICC'09. IEEE International Conference on, 1-5, 2009 | 14 | 2009 |
| Hardware and applications of AsAP: An asynchronous array of simple processors B Baas, Z Yu, M Meeuwsen, O Sattari, R Apperson, E Work, J Webb, ... IEEE HotChips Symposium on High-Performance Chips (HotChips 2006), 2006 | 12 | 2006 |
| Massively parallel processor array for mid-/back-end ultrasound signal processing DN Truong, BM Baas 2010 Biomedical Circuits and Systems Conference (BioCAS), 274-277, 2010 | 8 | 2010 |
| A 167-processor computational array for highly-efficient DSP and embedded application processing D Truong, W Cheng, T Mohsenin, Z Yu, T Jacobson, G Landge, ... HotChips Symp. High-Performance Chips, 2008 | 8 | 2008 |
| Circuit modeling for practical many-core architecture design exploration DN Truong, BM Baas Proceedings of the 47th Design Automation Conference, 627-628, 2010 | 2 | 2010 |
| A Dynamically-Configurable 16–4096-Point 65 nm Complex FFT Processor AT Jacobson, DN Truong, BM Baas | | |
Zhiyi YuAssociate Professor of Microelectronics, Fudan UniversityEmail verificata su fudan.edu.cn