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Jahoon Jin
Jahoon Jin
Postdoc, imec
Подтвержден адрес электронной почты в домене imec.be
Название
Процитировано
Процитировано
Год
A 0.75–3.0-Gb/s dual-mode temperature-tolerant referenceless CDR with a deadzone-compensated frequency detector
J Jin, X Jin, J Jung, K Kwon, J Kim, JH Chun
IEEE Journal of Solid-State Circuits 53 (10), 2994-3003, 2018
252018
A 4.0-10.0-Gb/s referenceless CDR with wide-range, jitter-tolerant, and harmonic-lock-free frequency acquisition technique
J Jin, J Kim, H Kim, C Piao, J Choi, DS Kang, JH Chun
ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference (ESSCIRC …, 2018
142018
A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization
J Jin, SM Lee, K Min, S Ju, J Lim, J Yook, J Lee, H Chae, K Kang, Y Hong, ...
IEEE Journal of Solid-State Circuits, 2023
62023
A 3nm GAAFET analog assisted digital LDO with high current density for dynamic voltage scaling mobile applications
S Kim, H Lee, Y Lee, D Lee, B Lee, J Jin, S Kim, M Noh, K Kang, S Kim, ...
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022
42022
A jitter-tolerant referenceless digital-CDR for cellular transceivers
J Kim, Y Ko, J Jin, J Choi, JH Chun
2020 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-4, 2020
42020
A 12.5-Gb/s near-ground transceiver employing a maxeye algorithm-based adaptation technique
J Jin, S Kim, X Jin, SH Kim, JH Chun
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (3), 522-530, 2017
32017
A 12.5-Gb/s near-GND transceiver for wire-line UHD video interfaces
S Kim, JM Kang, X Jin, SU Park, JH Jin, KW Kwon, JH Chun, JH Lee, ...
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 1488-1491, 2014
32014
A 20Gb/s/pin Single-Ended PAM-4 Transceiver with Pre/Post-Channel Switching Jitter Compensation and DQS-Driven Biasing for Low-Power Memory Interfaces
K Min, J Jin, SM Lee, S Ju, J Yook, J Lee, Y Hong, SS Park, SH Kim, J Lee, ...
2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2024
12024
Self-bias signal generating circuit using differential signal and receiver including the same
MIN Kyunghwan, JIN Jahoon, S Lee, S Kim, J Lim, S Ju, C Hyunsu
US Patent App. 18/058,584, 2023
12023
A 16/32 Gb/s dual-mode NRZ/PAM4 voltage-mode transmitter with 2-tap FFE
SH Kim, B Cho, J Jin, YH Song, JH Chun
IEEE Access 10, 119140-119149, 2022
12022
A Referenceless Digital CDR with a Half-Rate Jitter-Tolerant FD and a Multi-Bit Decimator
J Kim, Y Ko, J Jin, J Choi, JH Chun
Electronics 11 (4), 537, 2022
12022
Dynamic slew-rate control for high uniformity and low power in LCD driver ICs
SP Choi, M Lee, J Jin, KW Kwon, JH Chun
JSTS: Journal of Semiconductor Technology and Science 14 (5), 688-696, 2014
12014
SERIAL INTERFACE RECEIVER AND OFFSET CALIBRATION METHOD THEREOF
J Jin, K Min, S Kim, H Kim, S Lee, S JU
US Patent App. 18/458,332, 2024
2024
Semiconductor device
JIN Jahoon, MIN Kyunghwan, S Lee, SH Kim, J Lim, S Ju, HS Chea
US Patent 12,074,738, 2024
2024
Frequency detector and operating method thereof
JIN Jahoon, S Kim, MIN Kyunghwan, S Lee, S Ju
US Patent App. 18/361,059, 2024
2024
Clock edge correcting device and operating method thereof
MIN Kyunghwan, S Kim, S Lee, S Ju, JIN Jahoon
US Patent App. 18/472,796, 2024
2024
The design of non‐stacked and symmetric XOR for high‐speed applications
M Park, J Jin, S Park, H Chun
Electronics Letters 59 (13), e12850, 2023
2023
A 5.0-to-12.5-Gb/s, 1.7-pJ/b, 0.66-μs Lock-time Reference-less Sub-sampling CDR with Beat Detection FLL in 28nm CMOS
W Park, J Jin, M Park, S Jung, JH Chun
2022 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-3, 2022
2022
A 17.5-Gb/s transceiver with a MaxEye-based autonomous adaptation
J Jin, X Jin, SH Kim, IH Kim, J Jung, K Kwon, JH Chun
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017
2017
Dual-Mode Reference-less Clock Data Recovery Algorithm
KW Kwon, JH Jin, JH Chun
Journal of the Institute of Electronics and Information Engineers 53 (5), 77-86, 2016
2016
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