| An O-tree representation of non-slicing floorplan and its applications PN Guo, CK Cheng, T Yoshimura Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 268-273, 1999 | 574 | 1999 |
| Corner block list: An effective and efficient topological representation of non-slicing floorplan X Hong, G Huang, Y Cai, J Gu, S Dong, CK Cheng, J Gu IEEE/ACM International Conference on Computer Aided Design. ICCAD-2000. IEEE …, 2000 | 477 | 2000 |
| Optimal wire sizing and buffer insertion for low power and a generalized delay model J Lillis, CK Cheng, TTY Lin IEEE Journal of Solid-State Circuits 31 (3), 437-447, 1996 | 411 | 1996 |
| Ratio cut partitioning for hierarchical designs YC Wei, CK Cheng IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1991 | 346 | 1991 |
| Towards efficient hierarchical designs by ratio cut partitioning YC Wei, CK Cheng 1989 IEEE International Conference on Computer-Aided Design. Digest of …, 1989 | 322 | 1989 |
| Module placement based on resistive network optimization CK Cheng, ES Kuh IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1984 | 249 | 1984 |
| An improved two-way partitioning algorithm with stable performance (vlsi) CK Cheng, YCA Wei IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1991 | 239 | 1991 |
| Advanced model order reduction techniques in VLSI design S Tan, L He Cambridge University Press, 2007 | 192 | 2007 |
| Replace: Advancing solution quality and routability validation in global placement CK Cheng, AB Kahng, I Kang, L Wang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 188 | 2018 |
| New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing J Lillis, CK Cheng, TTY Lin, CY Ho Proceedings of the 33rd annual Design Automation Conference, 395-400, 1996 | 171 | 1996 |
| Floorplanning using a tree representation PN Guo, T Takahashi, CK Cheng, T Yoshimura IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2001 | 136 | 2001 |
| ePlace: Electrostatics-based placement using fast fourier transform and Nesterov's method J Lu, P Chen, CC Chang, L Sha, DJH Huang, CC Teng, CK Cheng ACM Transactions on Design Automation of Electronic Systems (TODAES) 20 (2 …, 2015 | 132 | 2015 |
| Performance-driven Steiner tree algorithm for global routing X Hong, T Xue, ES Kuh, CK Cheng, J Huang Proceedings of the 30th international Design Automation Conference, 177-181, 1993 | 121 | 1993 |
| Area minimization of power distribution network using efficient nonlinear programming techniques X Wu, X Hon, Y Ca, CK Cheng, J Gu, W Dai IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE …, 2001 | 120 | 2001 |
| A general purpose multiple way partitioning algorithm CW Yeh, CK Cheng, TTY Lin Proceedings of the 28th ACM/IEEE Design Automation Conference, 421-426, 1991 | 120 | 1991 |
| Floorplan representations: Complexity and connections B Yao, H Chen, CK Cheng, R Graham ACM Transactions on Design Automation of Electronic Systems (TODAES) 8 (1 …, 2003 | 108 | 2003 |
| Interconnect delay driven placement and routing of an integrated circuit design CK Cheng, SZ Yao US Patent 6,327,693, 2001 | 106 | 2001 |
| Block placement with symmetry constraints based on the O-tree non-slicing representation Y Pang, F Balasa, K Lampaert, CK Cheng Proceedings of the 37th Annual Design Automation Conference, 464-467, 2000 | 103 | 2000 |
| An enhanced perturbing algorithm for floorplan design using the O-tree representation Y Pang, CK Cheng, T Yoshimura Proceedings of the 2000 international symposium on physical design, 168-173, 2000 | 103 | 2000 |
| ePlace-MS: Electrostatics-based placement for mixed-size circuits J Lu, H Zhuang, P Chen, H Chang, CC Chang, YC Wong, L Sha, D Huang, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 98 | 2015 |