| Full copper wiring in a sub-0.25/spl mu/m CMOS ULSI technology D Edelstein, J Heidenreich, R Goldblatt, W Cote, C Uzoh, N Lustig, ... International Electron Devices Meeting. IEDM Technical Digest, 773-776, 1997 | 681 | 1997 |
| Copper metallization for high performance silicon technology R Rosenberg, DC Edelstein, CK Hu, KP Rodbell Annual review of materials science 30 (1), 229-262, 2000 | 592 | 2000 |
| Method for low temperature chemical vapor deposition of low-k films using selected cyclosiloxane and ozone gases for semiconductor applications RA Conti, DC Edelstein, GY Lee US Patent 7,084,079, 2006 | 554 | 2006 |
| RF circuit design aspects of spiral inductors on silicon JN Burghartz, DC Edelstein, M Soyuer, HA Ainspan, KA Jenkins IEEE Journal of Solid-State Circuits 33 (12), 2028-2034, 1998 | 377 | 1998 |
| Dual etch stop/diffusion barrier for damascene interconnects DC Edelstein, TJ Dalton, JG Gaudiello, M Krishnan, SG Malhotra, ... US Patent 6,153,935, 2000 | 331 | 2000 |
| Method for forming encapsulated metal interconnect structures in semiconductor integrated circuit devices SC Seo, C Sambucetti, X Chen, Z Chen, V McGahay, D Edelstein US Patent App. 10/026,176, 2003 | 299 | 2003 |
| On-chip wiring design challenges for gigahertz operation A Deutsch, PW Coteus, GV Kopcsay, HH Smith, CW Surovic, BL Krauter, ... Proceedings of the IEEE 89 (4), 529-555, 2001 | 280 | 2001 |
| Method for forming Co-WP-Au films CJ Sambucetti, JM Rubino, DC Edelstein, C Cabral Jr, GF Walker, ... US Patent 6,323,128, 2001 | 272 | 2001 |
| Silicon chip carrier with conductive through-vias and method for fabricating same DC Edelstein, PS Andry, LP Buchwalter, JA Casey, SA Goma, RR Horton, ... US Patent 7,276,787, 2007 | 267 | 2007 |
| Copper interconnection structure incorporating a metal seed layer DC Edelstein, JME Harper, CK Hu, AH Simon, CE Uzoh US Patent 6,181,012, 2001 | 224 | 2001 |
| Integrated circuit inductor JN Burghartz, DC Edelstein, CV Jahnes, CE Uzoh US Patent 5,884,990, 1999 | 217 | 1999 |
| Microelectronic structure including air gap DC Edelstein, DV Horak, EE Huang, SV Nitta, T Nogami, S Ponoth, ... US Patent 8,288,268, 2012 | 204 | 2012 |
| Spiral inductors and transmission lines in silicon technology using copper-damascene interconnects and low-loss substrates JN Burghartz, DC Edelstein, KA Jenkiin, YH Kwark IEEE Transactions on Microwave Theory and Techniques 45 (10), 1961-1968, 1997 | 204 | 1997 |
| Integrated circuit toroidal inductor JN Burghartz, DC Edelstein, CV Jahnes, CE Uzoh US Patent 5,793,272, 1998 | 201 | 1998 |
| Advantages of copper interconnects DC Edelstein Proceedings of the 12th International IEEE VLSI Multilevel Interconnection …, 1995 | 199 | 1995 |
| VLSI on-chip interconnection performance simulations and measurements DC Edelstein, GA Sai-Halasz, YJ Mii IBM Journal of Research and Development 39 (4), 383-401, 1995 | 192 | 1995 |
| Integrated circuit spiral inductor JN Burghartz, DC Edelstein, CV Jahnes, CE Uzoh US Patent 6,114,937, 2000 | 171 | 2000 |
| Apparatus and method for the electrochemical etching of a wafer M Datta, DC Edelstein, CE Uzoh US Patent 6,103,096, 2000 | 158 | 2000 |
| Nitride-enriched oxide-to-oxide 3D wafer bonding DC Edelstein, CC Yang US Patent 9,496,239, 2016 | 157 | 2016 |
| 'Length tuning of SPOPO' DC Edelstein, ES Wachman, CL Tang Appl. Phys. Lett 54, 1728, 1989 | 155 | 1989 |