| BRein memory: A single-chip binary/ternary reconfigurable in-memory deep neural network accelerator achieving 1.4 TOPS at 0.6 W K Ando, K Ueyoshi, K Orimo, H Yonekawa, S Sato, H Nakahara, ... IEEE Journal of Solid-State Circuits 53 (4), 983-994, 2017 | 184 | 2017 |
| A lightweight YOLOv2: A binarized CNN with a parallel support vector regression for an FPGA H Nakahara, H Yonekawa, T Fujii, S Sato Proceedings of the 2018 ACM/SIGDA International Symposium on field …, 2018 | 164 | 2018 |
| A fully connected layer elimination for a binarized convolutional neural network on an FPGA H Nakahara, T Fujii, S Sato 2017 27th International Conference on Field Programmable Logic and …, 2017 | 125 | 2017 |
| BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS K Ando, K Ueyoshi, K Orimo, H Yonekawa, S Sato, H Nakahara, M Ikebe, ... 2017 Symposium on VLSI Circuits, C24-C25, 2017 | 96 | 2017 |
| A random forest using a multi-valued decision diagram on an FPGA H Nakahara, A Jinguji, S Sato, T Sasao 2017 IEEE 47th international symposium on multiple-valued logic (ISMVL), 266-271, 2017 | 44 | 2017 |
| An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA H Nakahara, H Yonekawa, S Sato 2017 international conference on field programmable technology (ICFPT), 168-175, 2017 | 38 | 2017 |
| Ultra-Fast NoC Emulation on a Single FPGA T Van Chu, S Sato, K Kise 25th International Conference on Field Programmable Logic and Applications …, 2015 | 32 | 2015 |
| Fast and cycle-accurate emulation of large-scale networks-on-chip using a single fpga TV Chu, S Sato, K Kise ACM Transactions on Reconfigurable Technology and Systems (TRETS) 10 (4), 1-27, 2017 | 29 | 2017 |
| A Study of an Infrastructure for Research and Development of Many-Core Processors K Uehara, S Sato, T Miyoshi, K Kise International Conference on Parallel and Distributed Computing, Applications …, 2009 | 29 | 2009 |
| A demonstration of FPGA-based you only look once version2 (YOLOv2) H Nakahara, M Shimoda, S Sato 2018 28th International Conference on Field Programmable Logic and …, 2018 | 26 | 2018 |
| All binarized convolutional neural network and its implementation on an FPGA M Shimoda, S Sato, H Nakahara 2017 International Conference on Field Programmable Technology (ICFPT), 291-294, 2017 | 26 | 2017 |
| FPGA-based training accelerator utilizing sparseness of convolutional neural network H Nakahara, Y Sada, M Shimoda, K Sayama, A Jinguji, S Sato 2019 29th International Conference on Field Programmable Logic and …, 2019 | 25 | 2019 |
| GUINNESS: A GUI based binarized deep neural network framework for software programmers H Nakahara, H Yonekawa, T Fujii, M Shimoda, S Sato IEICE TRANSACTIONS on Information and Systems 102 (5), 1003-1011, 2019 | 21 | 2019 |
| A ternary weight binary input convolutional neural network: Realization on the embedded processor H Yonekawa, S Sato, H Nakahara 2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL), 174-179, 2018 | 21 | 2018 |
| A threshold neuron pruning for a binarized deep neural network on an FPGA T Fujii, S Sato, H Nakahara IEICE TRANSACTIONS on Information and Systems 101 (2), 376-386, 2018 | 21 | 2018 |
| An FPGA realization of a deep convolutional neural network using a threshold neuron pruning T Fujii, S Sato, H Nakahara, M Motomura Applied Reconfigurable Computing: 13th International Symposium, ARC 2017 …, 2017 | 21 | 2017 |
| An acceleration of a random forest classification using Altera SDK for OpenCL H Nakahara, A Jinguji, T Fujii, S Sato 2016 International Conference on Field-Programmable Technology (FPT), 289-292, 2016 | 19 | 2016 |
| Fast EUV lithography simulation using convolutional neural network H Tanabe, S Sato, A Takahashi Journal of Micro/Nanopatterning, Materials, and Metrology 20 (4), 041202-041202, 2021 | 17 | 2021 |
| An FPGA Realization of a Random Forest with k-Means Clustering Using a High-Level Synthesis Design A Jinguji, S Sato, H Nakahara IEICE TRANSACTIONS on Information and Systems 101 (2), 354-362, 2018 | 16 | 2018 |
| An FPGA realization of OpenPose based on a sparse weight convolutional neural network J Akira, T Fujii, S Sato, H Nakahara 2018 International Conference on Field-Programmable Technology (FPT), 310-313, 2018 | 13 | 2018 |
