適用於公開取用強制性政策的文章 - Rolf Drechsler瞭解詳情
未在任何資料庫公開的文章：50
RISC-V based virtual prototype: An extensible and configurable platform for the system-level
V Herdt, D Große, P Pieper, R Drechsler
Journal of Systems Architecture 109, 101756, 2020
授權規定： German Research Foundation, Federal Ministry of Education and Research, Germany
Analyzing inconsistencies in UML/OCL models
N Przigoda, R Wille, R Drechsler
Journal of Circuits, Systems and Computers 25 (03), 1640021, 2016
授權規定： German Research Foundation
Time-resolved detection of diffusion limited temperature gradients inside single isolated burning droplets using rainbow refractometry
CD Rosebrock, S Shirinzadeh, M Soeken, N Riefler, T Wriedt, R Drechsler, ...
Combustion and Flame 168, 255-269, 2016
授權規定： German Research Foundation
Automatic TLM fault localization for SystemC
HM Le, D Große, R Drechsler
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012
授權規定： German Research Foundation
SyReC: A hardware description language for the specification and synthesis of reversible circuits
R Wille, E Schönborn, M Soeken, R Drechsler
Integration 53, 39-53, 2016
授權規定： German Research Foundation, European Commission
On optimization-based ATPG and its application for highly compacted test sets
S Eggersglüß, K Schmitz, R Krenz-Bååth, R Drechsler
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016
授權規定： German Research Foundation
Incremental solving techniques for SAT-based ATPG
D Tille, S Eggersgluss, R Drechsler
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010
授權規定： German Research Foundation
Security validation of VP-based SoCs using dynamic information flow tracking
M Goli, M Hassan, D Große, R Drechsler
it-Information Technology 61 (1), 45-58, 2019
授權規定： German Research Foundation, Federal Ministry of Education and Research, Germany
Upper bounds for reversible circuits based on Young subgroups
N Abdessaied, M Soeken, MK Thomsen, R Drechsler
Information Processing Letters 114 (6), 282-286, 2014
授權規定： Danish Council for Strategic Research
Non-clausal SAT and ATPG
R Drechsler, T Junttila, I Niemelä
Handbook of satisfiability, 1047-1086, 2021
授權規定： German Research Foundation, Academy of Finland, Federal Ministry of …
GenMul: Generating Architecturally Complex Multipliers to Challenge Formal Verification Tools
A Mahzoon, D Große, R Drechsler
Recent Findings in Boolean Techniques: Selected Papers from the 14th …, 2021
授權規定： German Research Foundation
Edge verification: Ensuring correctness under resource constraints
R Drechsler, C Dominik
2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems …, 2021
授權規定： German Research Foundation
Benefits of illustrations and videos for technical documentations
CS Große, L Jungmann, R Drechsler
Computers in Human Behavior 45, 109-120, 2015
授權規定： German Research Foundation
PREASC: Automatic portion resilience evaluation for approximating SystemC-Based designs using regression analysis techniques
M Goli, R Drechsler
ACM Transactions on Design Automation of Electronic Systems (TODAES) 25 (5 …, 2020
授權規定： German Research Foundation, Federal Ministry of Education and Research, Germany
SAT-based ATPG for reversible circuits
H Zhang, R Wille, R Drechsler
2010 5th International Design and Test Workshop, 149-154, 2010
授權規定： German Research Foundation
Impacts of Creating Smart Everyday Objects on Young Female Students' Programming Skills and Attitudes
M Seraj, ES Katterfeldt, S Autexier, R Drechsler
Proceedings of the 51st ACM Technical Symposium on Computer Science …, 2020
授權規定： Federal Ministry of Education and Research, Germany
The complexity of error metrics
O Keszocze, M Soeken, R Drechsler
Information Processing Letters 139, 1-7, 2018
授權規定： German Research Foundation, European Commission
Towards a verification flow across abstraction levels verifying implementations against their formal specification
P Gonzalez-de-Aledo, N Przigoda, R Wille, R Drechsler, P Sanchez
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016
授權規定： German Research Foundation, Government of Spain
Debugging reversible circuits
R Wille, D Große, S Frehse, GW Dueck, R Drechsler
Integration 44 (1), 51-61, 2011
授權規定： German Research Foundation
Clocks vs. instants relations: Verifying CCSL time constraints in UML/MARTE models
J Peters, N Przigoda, R Wille, R Drechsler
2016 ACM/IEEE International Conference on Formal Methods and Models for …, 2016
授權規定： German Research Foundation, Federal Ministry of Education and Research, Germany
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